1. Field of the Invention
The present invention relates to an image pickup apparatus in which a multilayer wiring layer including a plurality of metal layers and insulating layers for insulating the metal layers is stacked on a substrate and a translucent cover is located on the multilayer wiring layer, and an endoscope including the image pickup apparatus.
2. Description of the Related Art
Conventionally, an electronic endoscope, a camera-equipped cellular phone, a digital camera, and the like including image pickup apparatuses provided with image pickup devices such as a CCD and a CMOS are well known.
In recent years, in the image pickup apparatuses, an image pickup apparatus of a wafer level chip size package (hereinafter referred to as WL-CSP) type is well known.
As a technique for completing packaging of a plurality of image pickup apparatuses using the WL-CSP, a manufacturing method explained below is known. First, a translucent cover glass wafer is stuck in a wafer level on a multilayer wiring layer of an image sensor wafer, on which a plurality of image pickup devices are formed, including a multilayer wiring layer including a plurality of metal layers and insulating layers for insulating the metal layers on a light receiving section and a peripheral circuit section of a substrate. Subsequently, through-wires that pierce through the image sensor wafer are respectively formed for each of the image pickup devices. Thereafter, connection electrodes to other apparatuses are formed for each of the image pickup devices in parts drawn out to a surface opposite to a surface of the image sensor wafer on which the translucent cover glass wafer is stuck in the respective through-wires. Finally, the image sensor wafer is separated into respective chips by dicing or the like for each of the image pickup devices.
The configuration and the manufacturing method of the image pickup apparatus by the WL-CSP explained above are disclosed in, for example, Japanese Patent Application Laid-Open Publication No. 2010-219402.
Conventionally, a configuration for reducing, in order to attain refining of a wire and an increase in speed of a signal, resistance of a wire by using Cu rather than conventionally-used Al in a plurality of metal layers functioning as wiring layers is well known.
In recent years, according to further progress of refining and a reduction in a pitch, in order to prevent a wiring delay due to parasitic capacitance that occurs among a plurality of metal layers, instead of silicon oxide-based films conventionally used in insulating layers, more specifically, a Tetraethyl orthosilicate (TEOS)-CVD film, a Spin-On Dielectrics (SOD) film, and the like, adoption of a low-dielectric insulating film having a lower relative dielectric constant, that is, a film called “Low-k insulating film” is ongoing.